Micro lead frame package and method to manufacture the micro lead frame package

ABSTRACT

The present invention comprises a lead frame substrate adapted to receive semiconductor die and multiple passive components. The lead frame substrate is preferably formed from a single piece of electrically conductive material, such as copper, and may be mounted within a lead frame package or directly onto a circuit board. The lead frame substrate includes mounting surfaces adapted to receive the semiconductor dice and passive components. The mounting surfaces are linked together by temporary and/or permanent connection bars. A method to manufacture the lead frame package includes, among other steps, forming a lead frame substrate, applying a molding compound to the lead frame substrate to fix each mounting surface and connection bar in place, removing the temporary connection bars, mounting the semiconductor components on the lead frame substrate, and applying a packaging material over the lead frame substrate to encapsulate the semiconductor components.

FIELD OF THE INVENTION

The present invention generally relates to the field of micro lead framedesign packaging and assembly. More specifically, the present inventioncomprises a micro lead frame substrate that is adapted to receive atleast one semiconductor die and multiple discrete passive componentswhich may be mounted within a lead frame or directly onto a circuitboard.

BACKGROUND OF THE INVENTION

Today's multi chip modules (MCM's) in power applications facesignificant challenges in terms of heat dissipation and heat management.Coupled with the need to dissipate heat in a uniform manner with lowthermal impedance, there is also a need to reduce space and cost.Traditional approaches to packaging MCM's have been in the form of aLand Grid Array (LGA) or Ball Grid Array (BGA) type substrate, whichconsist of multiple chips (semiconductor dice) plus passive componentsplaced on a laminate substrate. The substrate material conventionallyhas a high-thermal impedance and, even with enhanced via technology forheat management, still falls short of the low thermal impedance of alead frame design.

A conventional lead frame device has excellent thermal conductance andoptimum heat dissipation with regard to the power component mountingsurfaces. But, a conventional lead frame design and manufacturingprocess limits its ability to have multiple passive components mountedwithin the package. Manufacturing a lead frame that is adapted toreceive a power semiconductor die and passive components is oftenassociated with long manufacturing times, increased expenses, and isgenerally not considered an efficient manufacturing option. Conventionallead frames are adapted to receive only power semiconductor dice. Thus,external components must be coupled to the lead frame to ensureoperational effectiveness, which also adds to both the cost (ofprocurement, placement, etc.) and the space of the customer's board.

FIGS. 1A-1B illustrate a conventional lead frame package 10. The leadframe includes a semiconductor die pad 14 and multiple leads 16 arrangedabout the periphery of the lead frame 10. A conventional method forproducing the leadless semiconductor chip package shown in FIGS. 1A-1Bcomprises the steps of: (1) attaching a semiconductor chip 12 onto thedie pad 14 of a lead frame 10, wherein the lead frame 10 comprises aplurality of leads 16 arranged about the periphery of the die pad 14;(2) wire-bonding the leads of the lead frame 10 to bonding pads on thesemiconductor chip (shown as wires 18 in FIG. 1 b); and (3) forming apackage body 20 over the semiconductor chip 12 and the lead frame 10 ina manner that each lead 16 of the lead frame 10 has at least a portion17 exposed from the bottom of the package body. This conventional leadframe package 10 only supports a single semiconductor chip 12. Thepackage 10 cannot support any passive components. Thus, the passivecomponents (e.g., resistors and capacitors) are necessarily external tothe package 10.

SUMMARY OF THE INVENTION

The proposed invention resolves many of these issues by providing a leadframe substrate that is adapted to receive discrete passive componentsand may be placed within a micro lead frame package or directly onto acircuit board, and further providing a method of manufacturing the leadframe.

An aspect of the present invention is to provide a lead frame packagethat is relatively low in cost, has a relatively simple construction,and integrates a power semiconductor die and passive components withinthe package. In one embodiment, a micro lead frame substrate (“MLFsubstrate”) that includes a semiconductor die pad electrically coupledto multiple termination pads is mounted on a lead frame. Thesemiconductor die pad is adapted to receive a power semiconductor die(e.g., a MOSFET), a controller ASIC, a PWM controller, or the like. Thetermination pads are adapted to receive discrete passive components(e.g., resistors and capacitors) or a bonding wire. All of thesemiconductor components are therefore located within the same package.

Another aspect of the present invention is to provide a package in whichthe MLF substrate may be configured to meet the specific packagerequirements. In one embodiment, the termination pads within the MLFsubstrate are linked together by a combination of temporary andpermanent connection bars. The temporary connection bars providerigidity to the MLF substrate and are eventually removed. The temporaryconnection bars do not provide an electrical connection betweentermination pads in the final lead frame package. The permanentconnection bars electrically couple the semiconductor die pads and thetermination pads together.

Yet, another aspect of the present invention is to provide a MLFsubstrate for a semiconductor package. In one embodiment, the lead frameincludes a housing with a center pad and leads around its periphery. TheMLF substrate mounts on the center pad of the lead frame and iselectrically coupled to the leads. Thus, the lead frame package includesdiscrete passive components and saves customer board space. In anotherembodiment, the MLF substrate is mounted directly onto the customerboard, so that heat generated by a power semiconductor die is dissipateddirectly into the customer board. In yet another embodiment, only thesemiconductor die pads and the leads of the MLF substrate contact thecustomer board. The bottom surface of the MLF substrate has a steppedfeature whereby the contact pads (e.g., power semiconductor die pads,controller pads, and leads) are thicker than the non-contact portions ofthe MLF substrate (e.g., permanent connection bars).

Still another aspect of the present invention is to provide a method formanufacturing a lead frame package that includes power semiconductordice and multiple passive components. In one embodiment, the MLFsubstrate is stamped out of a single piece of material. Alternatively,the MLF substrate may be formed by an etching or laser manufacturingprocess. A molding compound is applied to the MLF substrate to supportthe semiconductor die and termination pads. The temporary connectionbars are preferably removed before the semiconductor components aremounted on the MLF substrate. In another embodiment, the temporaryconnection bars are removed after the semiconductor components aremounted on the MLF substrate. The semiconductor components are mountedonto the MLF substrate by a surface mount technology.

Another aspect of the present invention is to manufacture a lead framepackage using the MLF substrate above, including the steps of applying amolding compound over the MLF substrate to provide support for thetermination pads, the semiconductor die pads, the temporary connectionbars, and the permanent connection bars. Once the molding compound hasbeen applied, the temporary connection bars may be removed. Each powersemiconductor die is mounted to a semiconductor die pad and the passivecomponents are mounted across specific termination pads. After thesemiconductor components are mounted and the termination pads andsemiconductor dice are wire bonded to leads, a mold material is appliedto the MLF substrate to encapsulate the semiconductor components andbonding wires.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B illustrate a conventional lead frame, according to the priorart;

FIG. 2 is a plan view of an embodiment of the MLF substrate, accordingto the present invention;

FIG. 3 is a partial plan view of the MLF substrate shown in FIG. 2, FIG.4 is a partial plan view of the MLF substrate shown in FIG. 2,illustrating the a molding compound material applied to the MLFsubstrate;

FIG. 5 is a plan view of the MLF substrate shown in FIG. 4, illustratingthe MLF substrate after the temporary connection bars have been removed;

FIG. 6 is a plan view of the MLF substrate shown in FIG. 5, illustratingseveral discrete passive components mounted on the MLF substrate;

FIG. 7 is a plan view of an embodiment of a lead frame packageincorporating the MLF substrate;

FIG. 8A-8C illustrate a second embodiment of the MLF substrate,according to the present invention; and

FIGS. 9A-9B illustrate a third embodiment of the MLF substrate,according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Several embodiments of the present invention will now be described withreference to FIGS. 2-9. In general, the present invention provides anMLF substrate that allows power semiconductor components, as well aspassive components, to be mounted within the same package. The inventioncan be applied to, but is not limited to, providing optimum thermalperformance within a package that requires multiple or single silicondie combined with single or multiple passive components. The inventionmay replace existing micro lead frame products that require externalpassives by placing the external components within the package, and thusreducing space and cost.

FIG. 2 illustrates a lead frame template 100 according to one embodimentof the present invention. The lead frame template 100 is preferablymanufactured from a single sheet of thermally and electricallyconductive material 101. Copper (Cu), a Cu-based alloy, iron-nickel(Fe—Ni), a Fe—Ni-based ally, or the like is preferably used as thematerial for the lead frame template 101. It is within the scope andspirit of the present invention for the lead frame template 100 tocomprise other materials. The single sheet of material 101 preferablyhas a surface material finish appropriate for soldering or applyingother electrically and thermally conductive adhesion materials (e.g.,conductive epoxy).

In this embodiment, four MLF substrates 102 have been formed into thesingle sheet of material 101. The lead frame template 100 may includemore than or fewer than four MLF substrates 102. By way of example only,each MLF substrate 102 may be created through a stamping, etching,milling or laser manufacturing process. Each MLF substrate 102 ispreferably attached to the single sheet of material 101 by more than onetemporary connection bar 104. The temporary connection bars 104 securethe MLF substrate 102 in place with respect to the single sheet ofmaterial 101. As will be described later, the temporary connection bars104 are eventually removed from each MLF substrate 102 and are notintended to provide an electrical connection between the semiconductorcomponents in the final package.

The configuration of each MLF substrate 102 may vary. The number ofsemiconductor components that will be mounted on an MLF substrate 102 isdictated by the design requirements of the semiconductor package. FIG. 2illustrates one embodiment of a MLF substrate 102. In this embodiment,the MLF substrate 102 includes semiconductor die pads 106 a, 106 b, 106c, termination pads 108, temporary connection bars 104, and permanentconnection bars 110. The termination pads 108 shown in FIG. 2 aresubstantially rectangular in shape. It is within the scope and spirit ofthe invention for the termination pads 108 to comprise other shapes,such as, but no limited to oval, square, or circular.

In general, the design or layout of each MLF substrate 102 may bepredetermined to meet the specific electrical requirements of thesemiconductor package. For example, if each MLF substrate 102 is stampedout of the sheet of material 101, the stamping die may be configured toproduce the exact number of semiconductor die pads 106 and terminationpads 108 required for the semiconductor package. A strip of the material101 is left between each MLF substrate 102 so that multiple MLFsubstrates 102 may be transported by a single sheet.

The termination pads 108 form a pattern or matrix within the MLFsubstrate 102. As discussed above, the pattern or matrix of terminationpads 108 may vary greatly. The termination pads 108 generally providetwo functions: (1) to provide a mounting surface for passive components(e.g., resistors R1, R2, R3, R4 shown in FIG. 6); and (2) to provide amounting surface for bonding wires 240. Regardless of the pattern, thetermination pads 108 are linked together by at least one temporaryconnection bar 104 and/or at least one permanent connection bar 110. Atermination pad 108 may be linked to an adjacent termination pad 108 bymore than one temporary connection bar 104 and/or more than onepermanent connection bar 110. Initially, the temporary connection bars104 and the permanent connection bars 110 provide rigidity to the MLFsubstrate 102.

FIG. 3 illustrates the connections between termination pads 108 in moredetail. In general, adjacent termination pads 108 may be linked togetherin one of two ways: (1) the adjacent termination pads 108 are linked bya temporary connection bar 104 (e.g., termination pads 108 a and 108 g);or (2) the adjacent termination pads 108 are linked by a permanentconnection bar 110 (e.g., termination pads 108 g and 108 h). More thanone temporary connection bar 104 and/or permanent connection bar 110 mayextend from a termination pad 108.

The portion of the MLF substrate 102 shown in FIG. 3 includes twelvetermination pads 108 a-108 l. The connections between several of thetermination pads 108 will now be described to provide examples of howthe termination pads 108 may be linked together. The termination pad 108a has four temporary connection bars 104 and one permanent connectionbar 110 extending from it. One temporary connection bar 104 links thetermination pad 108 a with the termination pad 108 b. A second temporaryconnection bar 104 links the termination pad 108 a to the terminationpad 108 g. The third and fourth temporary connection bars 104 link thetermination pad 108 a to a permanent connection bar 110 that is adjacentto the termination pad 108 a. The permanent connection bar 110 links thetermination pad 108 a with the termination pad 108 i. The four temporaryconnection bars 104 fix the termination pad 108 a in place with respectto the surrounding elements of the MLF substrate 102 (e.g., terminationpads 108, 108 g) and create an electrical connection between the sameelements.

The termination pad 108 f illustrates that a termination pad 108 may belinked by fewer connection bars. The termination pad 108 f is linked tothe termination pad 108 e by a permanent connection bar 110 and islinked to the termination pad 108 l by a temporary connection bar 104.The permanent connection bar 110 and temporary connection bar 104 fixthe termination pad 108 e in place. In general, adjacent terminationpads 108 are connected together by a single connection bar. It is withinthe scope and spirit of the present invention to link adjacenttermination pads together by more than one connection bar.

Adjacent termination pads 108 may be linked together by all temporaryconnection bars 104 or all permanent connection bars 110. For example,the termination pad 108 l is linked to adjacent termination pads by fourtemporary connection bars 104. Alternatively, the termination pad 108 eis linked to adjacent termination pads only by permanent connection bars110. Each temporary connection bar 104 is shown as having a differentshape than the permanent connection bars 110 simply to illustrate whichconnection bars are temporary and which connection bars are permanent.It is within the spirit and scope of the present invention for thetemporary and permanent connection bars 104, 110 to have the same shapeor have a shape other than that shown in FIG. 3.

FIG. 4 illustrates a molding compound 112 applied to the MLF substrate102. The molding compound 112 fixes each components within the MLFsubstrate 102 (e.g., termination pads 108, semiconductor die pads 106,and connection bars 104, 110) in the molding compound 112. In apreferred embodiment, the molding compound 112 fills in the empty spacesor gaps throughout the MLF substrate 102. The gaps in the MLF substrate102 are defined by the areas in which a semiconductor die pad 106, atermination pad 108, or the connection bars 104, 110 are not locatedwithin the MLF substrate 102. The molding compound 112 providesadditional rigidity to the MLF substrate 102 in addition to thepermanent connection bars 110 and the temporary connection bars 104. Themolding compound 112 is preferably an epoxy-resin or anotherelectrically insulating material.

The molding compound 112, when applied to the MLF substrate 102,preferably does not cover the top or bottom surface of the semiconductordie pads 106 or the termination pads 108, since they provide mountingsurfaces for the semiconductor dice and passive components. The moldingcompound 112 is therefore preferably thinner than the sheet of material101. If the molding compound 112 initially covers a semiconductor diepad 106 or a termination pad 108, the surface of the pad may be milledor etched to remove the molding compound 112. In a preferred embodiment,the temporary connection bars 104 and permanent connection bars 110 arenot covered by the molding compound 112 either. However, it is withinthe spirit and scope of the present invention to cover the temporary andpermanent connection bars 104, 110 with the molding compound 112.

FIG. 5 illustrates that the temporary connection bars 104 are preferablyremoved from the MLF substrate 102, after the molding compound 112 hasbeen applied. Thus, the components of the MLF substrate 102 (e.g., thetermination pads 108, the permanent connection bars 110, andsemiconductor die pads 106) are held in place primarily by the moldingcompound 112. As shown in FIG. 5, a termination pad 108, if linked to anadjacent termination pad 108 at all, is linked only by a permanentconnection bar 110. The remaining permanent connection bar 110 providesan electrical connection between the linked termination pads 108. Forexample, the termination pad 108 a initially had four temporaryconnection bars 104 and one permanent connection bar 110 extending fromit when the MLF substrate 102 was initially formed (see FIGS. 2-3). Oncethe temporary connection bars 104 are removed, the termination pad 108 ais only linked to the termination pad 108 i by a single permanentconnection bar 110.

The temporary connection bars 104 may be removed at later stages of themanufacturing process. The temporary connection bars 104 simply must beremoved prior to electrical testing of the package. Otherwise, thetemporary connection bars 104 will provide unwanted electricalconnections between termination pads 108. In an alternative embodiment,the temporary connection bars 104 are removed through a back etchingprocess after the semiconductor components are mounted on the MLFsubstrate 102 (discussed later).

An adhesive tape (not shown), preferably made of epoxy resin, polyamideresin, polyester resin or the like, may be attached to the bottomsurface of the MLF substrate 102 to further stabilize the MLF substrate102. Adhesive tape is known to persons skilled in the art and does notrequire further disclosure. If an adhesive tape is applied to the MLFsubstrate 102, it is preferably applied to the MLF substrate 102 priorto mounting the semiconductor components on the MLF substrate 102.

After the tape is applied to the bottom surface (see FIG. 8B) of the MLFsubstrate 102, the semiconductor elements are mounted to the top side(see FIG. 8B) of the MLF substrate 102. There are many methods knownwithin the art for mounting semiconductor components within a package.By way of example only, the MLF substrate 102 may be screen-printed witha solder paste in a pattern that corresponds to the pattern of thepassive components that will be mounted on the termination pads 108.Each passive component is then positioned on a corresponding pair oftermination pads 108 and the solder is reflowed using conventionalsurface mount technology. Alternatively, the mounting surfaces of thepassive components may be printed with solder paste and then mounted onthe pair of termination pads 108. Other methods for mountingsemiconductor components are known within the art and do not requirefurther disclosure.

FIG. 6 illustrates one embodiment of the MLF substrate 102 with passivecomponents disposed between several of the termination pads 108. In thisembodiment, the resistors R1, R2, R3, R4 are disposed between several ofthe termination pads 108. Each resistor is electrically connected by itsleads on a termination pad 108. For example, the resistor R1 isconnected by its lead E1 to the termination pad 108 a and is connectedto the termination pad 108 g by its lead E2. Similarly, the resistor R2is connected by its lead E1 to the termination pad 108 h and isconnected to the termination pad 108 i by its lead E2.

As previously discussed, the termination pads 108 a and 108 i and thetermination pads 108 g and 108 h are each electrically coupled togetherby a permanent connection bar 110. The resistor R1 electrically couplesthe termination pads 108 a and 108 g together. The resistor R2electrically couples the termination pads 108 h and 108 i together. Theresistors R1 and R2 are thus electrically coupled together. Theresistors R3 and R4 are similarly electrically coupled together.

In this embodiment, passive components are not mounted on thetermination pads 108 b, 108 c, 108 f, 108 l. Thus, the termination pads108 b, 108 c, 108 f, 108 l provide mounting surfaces for bonding wires.Bonding wires 240, such as a gold wires, are connected between eachtermination pad 108 b, 108 c, 108 f, and 108 l and an external lead 232(see FIG. 7) of the semiconductor package 200 using a conventionalwire-bonding process.

Each semiconductor die pad 106 is adapted to receive a powersemiconductor die 210 (e.g., a MOSFET or a controller device 212 (e.g.,a PWM controller, a controller ASIC, etc.). The power semiconductor dice210 and controller devices 212 may be mounted on each semiconductor diepad 106 prior to or after the passive components (e.g., R1-R4) aremounted on the MLF substrate 102. As shown in FIG. 7, the MLF substrate102 includes two power semiconductor dice 210—one mounted on thesemiconductor die pad 106 b and one mounted on the semiconductor die pad106 c. A controller device 212 is mounted on the semiconductor die pad106 a. Each power semiconductor die 210 includes bonding pads (notshown). Bonding wires 240 electrically connect the bonding pads of thepower semiconductor die 210 to the leads 232 of the lead frame 230. Theembodiment shown in FIG. 7 is merely illustrative. The configuration ofthe semiconductor package 200 may vary according to the performancerequirements of the package.

The top surface of the MLF substrate 102 is sealed with a moldingmaterial after the passive components, the power semiconductor dice 210,and the controller devices 212 are mounted on the MLF substrate 102 andthe wire bonding is complete. After the molding material is cured, theadhesive tape is removed from the bottom surface of the MLF substrate102.

As previously discussed, the temporary connection bars 104 do not haveto be removed from the MLF substrate 102 immediately after the moldingcompound 112 is applied to the MLF substrate 102. The temporaryconnection bars 104 may remain within the MLF substrate 102 through allof the manufacturing steps discussed above. In an alternativeembodiment, the temporary connection bars 104 are removed after theadhesive tape is removed from the MLF substrate 102. A back etchingprocess is performed after the tape is removed to remove the temporaryconnection bars 104 from the MLF substrate 102. The back etching processcreates holes in the molding material 112 where the temporary connectionbars 104 were removed. The holes are preferably filled in by applyingadditional molding compound to the back side of the MLF substrate 102.

FIG. 7 illustrates a lead frame package 200 that incorporates the MLFsubstrate 102. The lead frame package 200 includes a housing 230 thathas leads 232 about its periphery. The sheet of material 101 iseventually divided into single units—each unit including a single MLFsubstrate 102. This process is commonly known within the industry assingulation. Each unit is then mounted on the housing 230. The leadframe package 200 is preferably encapsulated in a package body in amanner such that the bottom surface of each lead 232 has at least aportion exposed from the bottom of the package body for making anexternal electrical connection. The molding material has been removed toillustrate the interior of the lead frame package 200.

The lead frame package 200 shown in FIG. 7 comprises two powersemiconductor dice 210. Each semiconductor die 210 may be attached tothe semiconductor die pad 106 by an adhesive such as silver paste andthe silver paste is cured after die attach. The active surface of eachsemiconductor die 210 includes a plurality of bonding pads (not shown).Each bonding pad is electrically connected to a lead 232 by a bondingwire 240. The termination pads 108 that do not have a passive componentmounted to it provide a mounting surface for the bond wires 240. Severalof the termination pads 108 are shown as electrically connected to alead 232 by a bonding wire 240. The configuration of the lead framepackage 200 shown in FIG. 7 may vary and is not intended to limit thescope of the present invention. The package 200 includes powersemiconductor components and passive components may then be mounted ontothe customer's circuit board.

FIGS. 8A-8C illustrate yet another embodiment of an MLF substrate. Inthis embodiment, the MLF substrate 302 mounts directly onto thecustomer's circuit board. The configuration of the MLF substrate 302 issubstantially similar to the MLF substrate 102 shown previously in FIGS.2-6. Components within the MLF substrate 302 that are similar to the MLFsubstrate 102 (e.g., termination pads 108, permanent connection bars110, etc.) retain the same reference numeral.

The MLF substrate 302 comprises a unitary construction from the sheet ofmaterial 301 similar to the MLF substrate 102. Regardless of themanufacturing process, each MLF substrate 302 shown in FIG. 8A includesan outer frame 304 that connects the MLF substrate 302 to the singlesheet of material 301 (see FIG. 9A). The outer frame 304 comprisespermanent leads 303 and temporary leads 305. The temporary leads 305 fixthe MLF substrate 302 and similar to the temporary connection bars 104,are eventually removed from the MLF substrate 302 before the MLFsubstrate 302 is electrically tested. The temporary connection bars 104and the temporary leads 305 may be removed simultaneously or atdifferent stages of the manufacturing process. As shown in FIGS. 8A and8C, the semiconductor dice 210 and the termination pads 108 electricallycouple directly to the permanent leads 303 via at least one bonding wire240.

Removing the temporary leads 305 from the MLF substrate 302, in effect,transforms the MLF substrate 302 into a leadless package (see FIG. 8C).The MLF substrate 302 may therefore mount directly on the customer'scircuit board. As previously discussed above, the molding material 112fills in the gaps of the MLF substrate and does not cover the bottomsurface of the semiconductor dies pads 106 or the bottom surface of theterminations pads 108. In this embodiment, the MLF substrate 302 has asubstantially uniform thickness, shown as h in FIG. 8B. Thus, the entirebottom surface 310 of MLF substrate 302 contacts the circuit board. Oneadvantage of the MLF substrate 302 is that the heat dissipated from eachpower semiconductor die 210 is transferred directly from its bottomsurface, through the semiconductor die pad 106, and onto the customer'scircuit board—providing low thermal resistance. A drawback, however, isthat the non-conductive portions of the MLF substrate 302 (e.g., moldingcompound 112) also contact the circuit board. A conventional practicewithin the industry is to run tracks or traces along the top surface ofthe circuit board, which, in this embodiment, is located under the MLFsubstrate 302. The entire bottom surface 310 of the MLF substrate 302contacts the circuit board, when the MLF substrate is mounted on thecircuit board with no space between the bottom surface 310 of the MLFsubstrate 302 and the top surface of the circuit board, a customercannot run traces along the top surface of the circuit board.

FIGS. 9A-9B illustrate still another embodiment of the MLF substrate302. In this embodiment, the bottom surface 310 of the MLF substrate 310has a stepped feature to allow a customer to run traces along the topsurface of the circuit board. FIG. 9A illustrates four MLF substrates302 formed into a single sheet of material 301. The lead frame template300 may include more than or fewer than four MLF substrates 302. By wayof example only, each MLF substrate 302 may be created through astamping, etching, milling or laser manufacturing process.

Regardless of the manufacturing process, each MLF substrate 302 shown inFIG. 9A is connected to the single sheet of material 301 by thepermanent leads 303 and the temporary leads 305. In contrast to the MLFsubstrate 302 shown in FIGS. 8A-8C, the MLF substrate shown in FIG. 9Bhas a stepped feature on the bottom or contact surface 312. In thisembodiment, only the pads that are required to operate the package(e.g., permanent leads 303 and semiconductor die pads 106) contact thecircuit board when the MLF substrate 302 is mounted on the circuitboard. The stepped feature of the MLF substrate 302 is preferably formedwhen the MLF substrate 302 is initially created. As shown in FIG. 9B,the bottom surface 312 of the MLF substrate 302 provides thesemiconductor die pads 106 permanent leads 103 that extends out furtherthan the molding material 112. When the MLF substrate 302 is mounted onthe circuit board, gaps 314, are created between leads 303, that tracescan be run between. The gaps 314 also provide advantages to cleaning thecircuit board. For example, the raised bottom surface of the MLFsubstrate 302 allows cleaning of the circuit board with standardcleaning equipment while minimizing the potential for trapping water,flux, etc. under the MLF substrate 302, which will lead to electromigration and the like.

The foregoing description of preferred embodiments of the presentinvention has been provided for the purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to precise forms disclosed. Obviously, many modifications andvariations will be apparent to practitioners skilled in the art. Theembodiments were chosen and described in order to best explain theprinciples of the invention and its practical application, therebyenabling others skilled in the art to understand the invention forvarious embodiment and with various modifications as are suited to theparticular use contemplated. It is intended that the scope of theinvention be defined by the following claims and their equivalents.

1. A lead frame substrate, comprising: a plurality of connection bars; asemiconductor die pad being adapted to receive a semiconductor die; aplurality of termination pads being linked together and to saidsemiconductor die pad by said plurality of connection bars, each one ofsaid plurality of termination pads being adapted to receive a passivecomponent and a bonding wire; and a molding compound fixing saidsemiconductor die pad, said plurality of termination pads, and saidplurality of connection bars together.
 2. The lead frame substrateaccording to claim 1, wherein said semiconductor die pad, said pluralityof termination pads, and said plurality of connection bars comprise athermally and electrically conductive material.
 3. The lead framesubstrate according to claim 2, wherein said thermally and electricallyconductive material comprises copper.
 4. The lead frame substrateaccording to claim 1, wherein said semiconductor die pad, said pluralityof termination pads, and said plurality of connection bars include a topand bottom surface.
 5. The lead frame substrate according to claim 4,wherein said molding compound leaves said top and bottom surfacesuncovered.
 6. The lead frame substrate according to claim 1, whereinsaid semiconductor die pad, said plurality of termination pads, and saidplurality of connection bars have a unitary construction from a commonpiece of material.
 7. The lead frame substrate according to claim 1,further comprising a plurality of leads located around a periphery ofthe lead frame substrate.
 8. The lead frame substrate according to claim1, wherein said plurality of connection bars electrically couple saidsemiconductor die pad to said plurality of termination pads.
 9. The leadframe substrate according to claim 1, wherein said plurality ofconnection bars electrically couples said plurality of termination padstogether.
 10. The lead frame substrate according to claim 1, whereinsaid plurality of connection bars comprises permanent connection barsand temporary connection bars.
 11. The lead frame substrate according toclaim 10, wherein said temporary connection bars are removed from thelead frame substrate prior to mounting the lead frame substrate on alead frame.
 12. The lead frame substrate according to claim 1, whereinthe lead frame substrate comprises a substantially uniform thickness.13. The lead frame substrate according to claim 1, wherein the leadframe substrate is adapted for being mounted to a circuit board.
 14. Thelead frame substrate according to claim 13, wherein only saidsemiconductor die pad and said plurality of leads contact the circuitboard when the lead frame substrate is mounted on the circuit board. 15.A lead frame package, comprising: a housing having a central portion anda plurality of leads located around a periphery of said housing; and alead frame substrate mounted on said central portion, said lead framesubstrate being electrically coupled to at least one of said pluralityof leads and including: a plurality of connection bars; a semiconductordie pad being adapted to receive a semiconductor die; a plurality oftermination pads, each one of said plurality of termination pads beingadapted to receive a passive component and a bonding wire, saidplurality of termination pads being linked together and to saidsemiconductor die pad by said plurality of connection bars; and amolding compound fixing said semiconductor die pad, said plurality oftermination pads, and said plurality of connection bars together. 16.The lead frame package according to claim 15, wherein said plurality ofconnection bars, said semiconductor die pad, and said plurality oftermination pads have a unitary construction from a common sheet ofconductive material.
 17. The lead frame package according to claim 16,wherein said sheet of material comprises copper.
 18. The lead framepackage according to claim 15, wherein said plurality of connection barselectrically couples said plurality of terminations pads together andsaid semiconductor die pad to said plurality of termination pads. 19.The lead frame package according to claim 15, wherein said plurality ofconnection bars comprises a combination of permanent connection bars anda plurality of temporary connection bars.
 20. The lead frame packageaccording to claim 19, wherein said temporary connection bars areremoved from said lead frame substrate prior to mounting said lead framesubstrate on said central portion.
 21. The lead frame package accordingto claim 15, wherein said semiconductor die pad, said plurality oftermination pads, and said plurality of connection bars include a topand bottom surface.
 22. The lead frame package according to claim 21,wherein said molding compound leaves said top and bottom surfacesuncovered.
 23. The lead frame package according to claim 21, furthercomprising a packaging material, said packaging material encapsulatessaid top surface of each one of said plurality of connections bars, ofsaid semiconductor die pad, of each one of said plurality of terminationpads, and said molding compound.
 24. The lead frame package according toclaim 15, wherein said lead frame substrate comprises a substantiallyuniform thickness.
 25. A lead frame package, comprising: a housinghaving a central portion and a plurality of leads located around aperiphery of said housing; a lead frame substrate mounted on saidcentral portion, said lead frame substrate being electrically coupled toat least one of said plurality of leads and including: a plurality ofsemiconductor die pads, each one of said plurality of semiconductor diespads being adapted to receive a semiconductor die; a plurality oftermination pads, each one of said plurality of termination pads beingadapted to receive a passive component and a bonding wire, a pluralityof connection bars linking together said plurality of termination padsand said semiconductor die pad; and a molding compound applied to saidlead frame substrate, said molding compound fixing said plurality ofsemiconductor die pads, said plurality of termination pads, and saidplurality of connection bars together.
 26. The lead frame packageaccording to claim 25, wherein said lead frame substrate comprises aunitary construction from a common sheet of conductive material.
 27. Thelead frame package according to claim 26, wherein said sheet of materialcomprises copper.
 28. The lead frame package according to claim 25,wherein said housing comprises a plastic material.
 29. The lead framepackage according to claim 25, wherein each one of said plurality ofsemiconductor die pads, each one of said plurality of termination pads,and each one of said plurality of connection bars includes a top andbottom surface.
 30. The lead frame package according to claim 29,wherein said molding compound leaves said top and bottom surfacesuncovered.
 31. The lead frame package according to claim 25, whereinsaid plurality of connection bars comprises a plurality of temporaryconnection bars and a plurality of permanent connection bars.
 32. Thelead frame package according to claim 31, wherein said temporaryconnection bars fix said plurality of termination pads in positionrelative to each other.
 33. The lead frame package according to claim25, wherein said lead frame substrate further comprises a plurality ofleads located around a periphery of the said lead frame substrate. 34.The lead frame package according to claim 33, wherein said moldingcompound fixes said plurality of leads in said molding compound.
 35. Alead frame substrate for mounting onto a circuit board, comprising: aplurality of leads located about a periphery of the lead framesubstrate; a plurality of connection bars; a plurality of semiconductordie pads, each one of said plurality of semiconductor die pads beingadapted to receive a semiconductor die; a plurality of termination pads,each one of said plurality of termination pads being adapted to receivea passive component and a bonding wire, said plurality of terminationpads being linked together and to said plurality of semiconductor diepads by said plurality of connection bars; and a molding compound fixingsaid plurality of semiconductor die pads, said plurality of terminationpads, said plurality of connection bars, and said plurality of leadstogether.
 36. The lead frame substrate according to claim 35, whereinonly said plurality of semiconductor die pads and said plurality ofleads contact the circuit board when the lead frame substrate is mountedon the circuit board.
 37. The lead frame substrate according to claim35, wherein said plurality of connection bars electrically couple saidplurality of semiconductor die pads to said plurality of terminationspads. 38 The lead frame substrate according to claim 35, wherein thelead frame substrate comprises a substantially uniform thickness. 39.The lead frame substrate according to claim 35, wherein said frame, saidplurality of connection bars, said plurality of semiconductor die pads,and said plurality of termination pads have a unitary construction froma common piece of conductive material.
 40. A lead frame package,comprising: a circuit board having a top surface including electricallyconductive and electrically non-conductive portions; and a lead framesubstrate mounted on said top surface of said circuit board, including:a plurality of leads located about a periphery of said lead framesubstrate; a plurality of connection bars; a semiconductor die pad beingadapted to receive a semiconductor die; a plurality of termination pads,each one of said plurality of termination pads being adapted to receivea passive component and a bonding wire, said plurality of terminationpads being linked together and to said semiconductor die pad by saidplurality of connection bars; and a molding compound fixing saidsemiconductor die pad, said plurality of termination pads, saidplurality of connection bars, and said plurality of leads together. 41.The lead frame package according to claim 40, wherein said plurality ofleads and said semiconductor die pad are electrically coupled to saidconductive portions of said circuit board.
 42. A method formanufacturing a lead frame substrate, the lead frame substrate beingconfigured to receive semiconductor dice and discrete passivecomponents, the method comprising the steps of: (a) forming a lead framesubstrate in a sheet of conductive material, the lead frame substrateincluding at least one semiconductor die pad, a plurality of terminationpads, and a plurality of temporary and permanent connection bars thatlink the semiconductor die pads and plurality of termination padstogether; (b) applying a molding compound to the lead frame substrateformed in said step (a), the molding compound fixing the semiconductordie pads, the plurality of termination pads, and the plurality oftemporary and permanent connection bars together; and (c) removing theplurality of temporary connection bars from the lead frame substrate.43. The method according to claim 42, wherein forming the lead framesubstrate in said step (a) is accomplished by a stamping process. 44.The method according to claim 42, wherein forming the lead framesubstrate in said step (a) is accomplished by an etching process. 45.The method according to claim 42, wherein removing the plurality oftemporary connection bars in said step (c) is accomplished by a stampingprocess.
 46. The method according to claim 42, wherein removing theplurality of temporary connection bars in said step (c) is accomplishedby an etching process.
 47. The method according to claim 42, whereinremoving the plurality of temporary connection bars in said step (c) isaccomplished by a laser cutting process.
 48. The method according toclaim 42, wherein removing the plurality of temporary connection bars insaid step (c) is accomplished by a milling process.
 49. A method formounting semiconductor components on a lead frame substrate, comprisingthe steps of: (a) forming a plurality of lead frame substrates into asheet of conductive material, each one of the plurality of lead framesubstrates includes at least one semiconductor die pad and a pluralityof termination pads linked together by a plurality of temporaryconnection bars and a plurality of permanent connection bars; (b)applying a molding compound to each one of the plurality of lead framesubstrates formed in said step (a); (c) removing the plurality oftemporary connection bars from each lead frame substrate; (d) applyingadhesive tape to the back side of each lead frame substrate; (e)mounting discrete passive components on the termination pads; (f)mounting a semiconductor die on each semiconductor die pad; (g)producing bonding connections; and (h) applying a packaging materialover each lead frame substrate formed in said step (a), the packagingmaterial encasing the discrete passive components mounted in said step(e), the semiconductor dice mounted in said step (f), and the bondingconnections produced in said step (g).
 50. The method according to claim49, further comprising: (i) separating the sheet of material intoindividual units, each one of the individual units containing a leadframe substrate.
 51. The method according to claim 49, wherein each leadframe substrate formed in said step (a) is accomplished by a stampingprocess.
 52. The method according to claim 49, wherein removing theplurality of temporary connection bars in said step (c) is accomplishedby an etching process.
 53. The method according to claim 49, whereinremoving the plurality of temporary connection bars in said step (c) isaccomplished by a laser cutting process.
 54. The method according toclaim 49, wherein removing the plurality of temporary connection bars insaid step (c) is accomplished by a milling process.
 55. The methodaccording to claim 49, wherein applying the molding compound in saidstep (b) further comprises fixing the semiconductor die pads, theplurality of termination pads, the plurality of temporary connectionbars, and the plurality of permanent connection bars in the moldingcompound.
 56. The method according to claim 49, wherein each lead framesubstrate formed in said step (a) is accomplished by an etching process.57. A method for mounting semiconductor components on a lead framesubstrate, comprising the steps of: (a) forming a plurality of leadframe substrates into a sheet of material, each one of the plurality oflead frame substrates including at least one semiconductor die pad and aplurality of termination pads, the semiconductor die pad and theplurality of termination pads being linked together by a plurality oftemporary connection bars and a plurality of permanent connection bars;(b) applying a molding compound to each one of the plurality of leadframes substrates formed in said step (a); (c) applying adhesive tape tothe backside of each lead frame substrate; (d) mounting discrete passivecomponents on the termination pads; (e) mounting a semiconductor die oneach semiconductor die pad; (f) producing bonding connections; (g)applying a packaging material over each lead frame substrate formed insaid step (a), the packaging material encasing the discrete passivecomponents mounted in said step (e), the semiconductor dice mounted insaid step (f), and the bonding connections produced in said step (g);(h) removing the adhesive tape that was applied in said step (c); and(i) applying an etching process to the backside of each lead framesubstrate to remove the plurality of temporary connection bars.
 58. Amethod for manufacturing a lead frame substrate, the lead framesubstrate being configured to receive semiconductor dice and discretepassive components, the method comprising the steps of: (a) forming alead frame substrate in a sheet of material, the lead frame substrateincluding at least one semiconductor die pad, a plurality of terminationpads, a plurality of temporary and permanent connection bars that linkthe semiconductor die pads and plurality of termination pads together,and a plurality of permanent and temporary leads; (b) applying a moldingcompound to the lead frame substrate formed in said step (a), themolding compound fixing the semiconductor die pads, the plurality oftermination pads, the plurality of temporary and permanent connectionbars, and the plurality of permanent and temporary leads together; and(c) removing the plurality of temporary connection bars and temporaryleads from the lead frame substrate.
 59. The method according to claim58, wherein forming the lead frame substrate in said step (a) createssemiconductor die pads and permanent leads that are thicker than thetermination pads, the temporary connection bars, and the temporaryleads.
 60. The method according to claim 58, wherein the plurality ofpermanent and temporary leads are located about a periphery of the leadframe substrate formed in said step (a).